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HT9172 dtmf receiver block diagram rev. 1.01 1 february 23, 2009 features operating voltage: 2.5v~5.5v minimal external component requirements no external filter required low standby current in power down mode) excellent performance tristate data output for mcu interface 3.58mhz crystal or ceramic resonator oscillator 1633hz can be inhibited by the inh pin 18-pin dip/sop packaging general description the HT9172 is a dual tone multi frequency (dtmf) re- ceiver device which includes an integrated digital de- coder and band split filter functions as well as power-down and inhibit mode operations. the device uses digital counting techniques to detect and decode the full range of 16 dtmf tone pairs into a 4-bit code output. highly accurate switched capacitor filters are uti- lised to divide the dtmf dual tone frequencies into low and high group signals. an integrated dial tone rejection circuit is provided to eliminate the need for pre-filtering.
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pin assignment pin description pin name i/o internal connection description vp i operational amplifier operational amplifier non-inverting input vn i operational amplifier inverting input gs o operational amplifier output terminal vreef o vref reference voltage output, normally v dd /2 x1 i oscillator the system oscillator consists of an inverter, a bias resistor and the required on-chip load capacitor. a standard 3.579545mhz crystal connected to the x1 and x2 terminals imple- ments the oscillator function. x2 o pwdn i cmos in pull-low active high. this enables the device to go into its power down mode and inhibits the oscillator. this pin input is pulled low internally. inh i cmos in pull-low active high. this inhibits the detection of tones representing characters a, b, c and d. this pin input is pulled low internally. vss negative power supply, ground oe i cmos in pull-high d0~d3 output enable, active high d0~d3 o cmos out tristate received data output terminals oe=h : output enable oe=l : high impedance dv o cmos out data valid output. when the device has received a valid dtmf tone, this line will go high; other- wise it remains low. est o cmos out early steering output - see functional description rt/gt i/o cmos in/out tone acquisition time and release time can be set through connection with ex- ternal resistor and capacitor. vdd positive power supply, 2.5v~5.5v for normal operation HT9172 rev. 1.01 2 february 23, 2009 5 6
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approximate internal connection circuits absolute maximum ratings supply voltage ..............................v ss 0.3v to v ss +6v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 2.5 5 5.5 v i dd operating current 5v 37ma i stb standby current 5v v pwdn =v dd , (not include pwdn pull-low current) 15 a v il input low voltage 5v 1.0 v v ih input high voltage 5v 4.0 v i il input low current 5v v vp =v vn =0v 0.1 a i ih input high current 5v v vp =v vn =5v 0.1 a r oe pull-high resistance (oe) 5v v oe =0v 70 110 160 k r pl pull-low resistance (inh, pwdn) 5v v inh =5.0v, v pwdn =5.0v 150 250 375 k r in input impedance (vn, vp) 5v 10 m i oh source current (d0~d3, est, dv) 5v v out =4.5v 0.4 0.8 ma i ol sink current (d0~d3, est, dv) 5v v out =0.5v 1.0 2.5 ma f osc system frequency 5v crystal=3.5795mhz 3.5759 3.5795 3.5831 mhz HT9172 rev. 1.01 3 february 23, 2009 ' 9 . / 0 3 ( 3 # 3 . / ( & & 3 0 / & 3 ( ! ' % $ % & : 0 0 . ( & : 0 & 3 ( 1 : 0 / . # 2 " # 2 2 " # & 3 ( ! '
a.c. characteristics f osc =3.5795mhz, ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions dtmf signal input signal level 3v 36 6 dbm 5v 29 1 twist accept limit (positive) 5v 10 db twist accept limit (negative) 5v 10 db dial tone tolerance 5v 18 db noise tolerance 5v 12 db third tone tolerance 5v 16 db frequency deviation acceptance 5v 1.5 % frequency deviation rejection 5v 3.5 % t pu power up time (see figure 4.) 5v 30 ms gain setting amplifier r in input resistance 5v 10 m i in input leakage current 5v v ss <(v vp ,v vn )100k 4.5 v pp r l load resistance (gs) 5v 50 k c l load capacitance (gs) 5v 100 pf v cm common mode range 5v no load 3.0 v pp steering control t dp tone present detection time 5v 5 11 14 ms t da tone absent detection time 5v 4 8.5 ms t acc acceptable tone duration 5v 42 ms t rej rejected tone duration 5v 20 ms t ia acceptable inter-digit pause 5v 42 ms t ir rejected inter-digit pause 5v 20 ms t pdo propagation delay (rt/gt to do) 5v 811 s t pdv propagation delay (rt/gt to dv) 5v 12 s t dov output data set up (do to dv) 5v 4.5 s t ddo disable delay (oe to do) 5v 300 ns t edo enable delay (oe to do) 5v 50 60 ns note: do=d0~d3 HT9172 rev. 1.01 4 february 23, 2009
HT9172 rev. 1.01 5 february 23, 2009 5 6
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2 2 ; 2 2 ; 2 # 0 2 " # 2 " # 2 # figure 1. test circuit functional description overview the HT9172 tone decoder consists of three band pass filters and two digital decode circuits to convert a dtmf tone into a digital code output. the device contains an operational amplifier to adjust the input signal level as shown in figure 2. the pre-filter is a band rejection filter which will reject frequencies between 350hz to 400hz. the low group filter, filters the low group frequency sig- nal output whereas the high group filter, filters the high group frequency signal output. each filter output is followed by a zero-crossing detector with incorporates hysteresis. when the signal amplitude at the output exceeds a specified level, it is transferred to a full swing logic signal. when the input signal is recognized as an effective dtmf tone, the dv line will go high, and the corre- sponding dtmf tone code will be generated. steering control circuit the steering control circuit is used to measure the effec- tive signal duration and for protecting against valid sig- nal drop out. this is achieved using an analog delay which is implemented using an external rc time-con- stant, controlled by the output line est. the timing diagram is shown in figure 3. the est pin is normally low and will pull the rt/gt pin low via the ex- ternal rc network. when a valid tone input is detected, the est pin will go high, which will in turn pull the rt/gt pin high through the rc network. when the voltage on rt/gt rises from 0 to v trt , which is 2.35v for a 5v power supply, the input signal is effec- tive, and the corresponding code will be generated by the code detector. after d0~d3 have been latched, dv will go high. when the voltage on rt/gt falls from vdd to v trt , i.e. when there is no input tone, the dv output will go low, and d0~d3 will maintain their present data until a next valid tone input is produced. by selecting suitable external rc values, the minimum acceptable input tone duration, t acc , and the minimum acceptable inter-tone rejection, t ir , can be set. the values of the external rc components, can be chosen using the following formula. also refer to figure 5 for details. t acc =t dp +t gtp ; t ir =t da +t gta ; where t acc : tone duration acceptable time t dp : est output delay time ( l
h) t gtp : tone present time t ir : inter-digit pause rejection time ( & / . # / /

! / 7 / / ( & / . # / / # figure 2. amplifier input application circuits
timing diagrams HT9172 rev. 1.01 6 february 23, 2009 3 3 / 0 . & 0 / 0 1 0 * 2 < * * . * * * * . * 0 / . = * * 0 * 0 0 9 0 + 9 0 / 0 * * * 0 + > 0 + figure 3. steering timing 0 4 * ( . & 0 0 : figure 4. power-up timing
figure 5. steering time adjustment circuits dtmf dialing matrix dtmf data output table low group (hz) high group (hz) digit oe d3 d2 d1 d0 697 1209 1 h l l l h 697 1336 2 h l l h l 697 1477 3 h l l h h 770 1209 4hlhl l 770 1336 5hlhlh 770 1477 6hlhhl 852 1209 7hlhhh 852 1336 8 h h l l l 852 1477 9 h h l l h 941 1336 0 h h l h l 941 1209 * h h l h h 941 1477 # h h h l l 697 1633 a h h h l h 770 1633 b hhhh l 852 1633 chhhhh 941 1633 d h l l l l any l z z z z note: z high impedance; any any digit HT9172 rev. 1.01 7 february 23, 2009 7 5 ?
2 6 8 @ - * / 4 / 4 / 4 / 4 7 7 / * * / 0 1 0 . & 0 * * (a) fundamental circuit: t gtp =r c ln (v dd /(v dd v trt )) t gta =r c ln (v dd /v trt ) / * * / 0 1 0 . & 0 / * * * (b) t gtp t gta : t gtp =r1 c ln (v dd /(v dd v trt )) t gta = (r1 // r2) c ln (v dd /v trt )
data output the data outputs, d0~d3, are tristate outputs. when the oe input is low, the d0~d3 data outputs, will be in a high im - pedance condition. application circuits application circuit 1 application circuit 2 HT9172 rev. 1.01 8 february 23, 2009 5 6
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6 5 8 * * / 0 1 0 . & 0 * * * * * 2 . ( & / . # 3 ( 4 * ( & & 2 # 2 2 ; * * 2 2 ; 2 2 ; 2 # * 0 # 0 % + a & & b 0 % + a 2 # . c d " e a f / f 6 2 ; / f 2 2 ; / f 6 2 ; / 7 f
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/ f / / 7 / 9 / 7 / 9 /
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/ a f f 0 % + a 2 # note: x tal = 3.579545mhz crystal c1=c2 20pf x tal = 3.58mhz ceramic resonator c1=c2 39pf note: x tal = 3.579545mhz crystal c1=c2 20pf x tal = 3.58mhz ceramic resonator c1=c2 39pf
package information 18-pin dip (300mil) outline dimensions ms-001d (see fig1) symbol dimensions in mil min. nom. max. a 880 920 b 240 280 c 115 195 d 115 150 e14 22 f45 70 g 100 h 300 325 i 430 ms-001d (see fig2) symbol dimensions in mil min. nom. max. a 845 880 b 240 280 c 115 195 d 115 150 e14 22 f45 70 g 100 h 300 325 i 430 HT9172 rev. 1.01 9 february 23, 2009
fig1. full lead packages
fig2. 1 / 2 lead packages
mo-095a (see fig2) symbol dimensions in mil min. nom. max. a 845 885 b 275 295 c 120 150 d 110 150 e14 22 f45 60 g 100 h 300 325 i 430 HT9172 rev. 1.01 10 february 23, 2009
18-pin sop (300mil) outline dimensions ms-013 symbol dimensions in mil min. nom. max. a 393 419 b 256 300 c12 20 c 447 463 d 104 e 50 f4 12 g1 6 50 h8 13 08 HT9172 rev. 1.01 11 february 23, 2009 2 8 - * . # b
product tape and reel specifications reel dimensions sop 18w symbol description dimensions in mm a reel outer diameter 330.0 1.0 b reel inner diameter 100.0 1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0 0.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.2 0.2 HT9172 rev. 1.01 12 february 23, 2009 - 0 0 *
carrier tape dimensions sop 18w symbol description dimensions in mm w carrier tape width 24.0 +0.3/-0.1 p cavity pitch 16.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5 0.1 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.9 0.1 b0 cavity width 12.0 0.1 k0 cavity depth 2.8 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 21.3 0.1 HT9172 rev. 1.01 13 february 23, 2009 * 4 2 * . # g 2 - 2 2 3 " ; $ " + % % + % d + /
HT9172 rev. 1.01 14 february 23, 2009 copyright 2009 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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